Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation

The Scalable Parallel Random Number Generators (SPRNG) library is widely used to generate random numbers in Monte Carlo simulations due to the good statistical properties of both its serial and parallel random number streams. In this paper, we suggest an efficient hardware architecture for the Parallel Additive Lagged-Fibonacci Generator (PALFG) provided by the SPRNG library. This design has been implemented on a VirtexII Pro FPGA device and runs at a clock speed of 125 MHz while delivering one 31-bit random number per clock. Compared to the SPRNG software algorithm executing on a Pentium 4 workstation, a single instance of our design offers a 2.3-fold performance improvement and appears to be 50 times more efficient.